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ispPAC-POWR6AT6
In-System Programmable Power Supply Monitoring and Margining Controller
April 2006 Preliminary Data Sheet
(R)
Features
Power Supply Margin and Trim Functions
* * * * Trim and margin up to six power supplies Dynamic voltage control through I2C Four hardware selectable voltage profiles Independent Digital Closed-Loop Trim function for each output
Application Block Diagram
Vout
3.3V
Trim Vout Trim Vout
Analog Input Monitoring
* Six analog monitor inputs * Differential input architecture for accurate remote ground sensing * 10-bit ADC for direct voltage measurements
1.8V
Trim Vout
POL#1
Trim Vout
POL#2
Trim Vout
2-Wire (I2C/SMBusTM Compatible) Interface
* Readout of the ADC * Dynamic trimming/margining control
POL#3
Trim
Other Features
* * * * * Programmable analog circuitry Wide supply range, 2.8V to 3.96V In-system programmable through JTAG Industrial temperature range: -40C to +85C 32-pin QFN package, only 5mm x 5mm, leadfree option
6 Analog Trim Outputs 6 Analog Monitor Inputs
ADC
Other Board Circuitry
2.5V
CPU
I 2C Bus
Description
Lattice's Power Manager II ispPAC-POWR6AT6 is a general-purpose power-supply monitoring and margining controller, incorporating in-system programmable analog functions implemented in non-volatile E2CMOS(R) technology. The ispPAC-POWR6AT6 device provides six independent analog input channels to monitor up to six power supply test points. Each of these input channels offers a differential input to support remote ground sensing. The ispPAC-POWR6AT6 incorporates six DACs for generating a trimming voltage to control the output voltage of a power supply. The trimming voltage can be set to four hardware selectable preset values (voltage profiles) or can be dynamically loaded in to the DAC through the I2C bus. Additionally, each power supply output voltage can be maintained typically within 0.5% tolerance across various load conditions using the Digital Closed Loop Control mode. The operating voltage profile can be selected using external hardware pins.
Power Supply Margin/Trim Control
I2 C Interface
ispPAC-POWR6AT6
The on-chip 10-bit A/D converter can both be used to monitor the VMON voltage through the I2C bus as well as for implementing digital closed loop mode for maintaining the output voltage of all power supplies controlled by the monitoring and trimming section of the ispPACPOWR6AT6 device. The I2C bus/SMBus interface allows an external microcontroller to measure the voltages connected to the VMON analog monitor inputs and load the DACs for the generation of the trimming voltages of the external DCDC converters.
(c) 2006 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
www.latticesemi.com
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6at6_01.0
Lattice Semiconductor
Figure 1. ispPAC-POWR6AT6 Block Diagram
CLTLOCK/SMBA
ispPAC-POWR6AT6 Data Sheet
CLTENb
VCCD
VMON1
Decoder TrimCell 1 DAC
VCCA
VPS0
VPS1
TRIM1
VMON1GS VMON2 VMON2GS VMON3 VMON3GS ADC VMON4 VMON4GS
OSC TrimCell 4 DAC Control Logic TrimCell 3 DAC Set Point Registers TrimCell 2 DAC
TRIM2
TRIM3
TRIM4
VMON5 VMON5GS VMON6 VMON6GS
TrimCell 6 DAC TrimCell 5 DAC
TRIM5
TRIM6
SCL
I 2C Interface
JTAG Interface
SDA ispPAC-POWR6AT6 GND VCCJ TDO TDI TCK TMS
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Lattice Semiconductor
ispPAC-POWR6AT6 Data Sheet
Pin Descriptions
Number 7 8 6 Name VPS0 VPS1 CLTENb Pin Type Digital Input Digital Input Digital Input Voltage Range VCCD VCCD VCCD Description Trim Select Input 0 Trim Select Input 1 Enables closed loop trim process (asserted low) Signals that all TrimCells selected for closedloop trim have reached a trim locked condition. Can be configured to be compliant with SMBus Alert protocol.2 Voltage Monitor 1 Input Voltage Monitor 1 Ground Sense Voltage Monitor 2 Input Voltage Monitor 2 Ground Sense Voltage Monitor 3 Input Voltage Monitor 3 Ground Sense Voltage Monitor 4 Input Voltage Monitor 4 Ground Sense Voltage Monitor 5 Input Voltage Monitor 5 Ground Sense Voltage Monitor 6 Input Voltage Monitor 6 Ground Sense Ground Core VCC, Main Power Supply Analog Power Supply VCC for JTAG Logic Interface Pins Trim DAC Output 1
3
9 15 14 17 16 19 18 21 20 23 22 25 24 32 12 13 2 31
CLTLOCK/ SMBA VMON1 VMON1GS VMON2 VMON2GS VMON3 VMON3GS VMON4 VMON4GS VMON5 VMON5GS VMON6 VMON6GS GND VCCD4 VCCA4 VCCJ TRIM1
Open Drain Output Analog Input Analog Input Analog Input Analog Input Analog Input Analog Input Analog Input Analog Input Analog Input Analog Input Analog Input Analog Input Ground Power Power Power Analog Output
1
0V to 5.5V -0.3V to 5.75V -0.3V to 0.3V -0.3V to 5.75V -0.3V to 0.3V3 -0.3V to 5.75V -0.3V to 0.3V3 -0.3V to 5.75V -0.3V to 0.3V3 -0.3V to 5.75V -0.3V to 0.3V3 -0.3V to 5.75V -0.3V to 0.3V3 Ground 2.8V to 3.96V 2.8V to 3.96V 2.25V to 3.6V -320mV to +320mV from Programmable DAC Offset -320mV to +320mV from Programmable DAC Offset -320mV to +320mV from Programmable DAC Offset -320mV to +320mV from Programmable DAC Offset -320mV to +320mV from Programmable DAC Offset -320mV to +320mV from Programmable DAC Offset
30
TRIM2
Analog Output
Trim DAC Output 2
29
TRIM3
Analog Output
Trim DAC Output 3
28
TRIM4
Analog Output
Trim DAC Output 4
27
TRIM5
Analog Output
Trim DAC Output 5
26
TRIM6
Analog Output
Trim DAC Output 6
3
Lattice Semiconductor
ispPAC-POWR6AT6 Data Sheet
Pin Descriptions (Cont.)
Number 1 3 5 4 10 11 Name TDO TCK TMS TDI SCL SDA Pin Type Digital Output Digital Input Digital Input Digital Input Digital Input Digital I/O Voltage Range Description JTAG Test Data Out JTAG Test Clock Input JTAG Test Mode Select; Internal Pullup JTAG Test Data In; Internal Pullup I2C Serial Clock Input I2C Serial Data, Bi-directional Pin
1. Open-drain outputs require an external pull-up resistor to a supply. 2. Normally asserted low, but can be programmed to assert high (open) if desired. 3. The VMONxGS inputs are the ground sense line for each given VMON pin. The VMON input pins along with the VMONxGS ground sense pins implement a differential pair for each voltage monitor to allow remote sense at the load. VMONxGS lines must be connected and are not to exceed -0.3V to +0.3V in reference to the GND pin. 4. VCCA and VCCD pins must be connected together on the circuit board.
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Lattice Semiconductor
ispPAC-POWR6AT6 Data Sheet
Absolute Maximum Ratings
Absolute maximum ratings are shown in the table below. Stresses beyond those listed may cause permanent damage to the device. Functional operation of the device at these or any other conditions beyond those indicated in the recommended operating conditions of this specification is not implied.
Symbol VCCD VCCA VCCJ VIN VMON+ VMONGS TS TA Core supply Analog supply JTAG logic supply Digital input voltage (all digital I/O pins) VMON input voltage VMON input voltage ground sense Storage temperature Ambient temperature Parameter Conditions Min. -0.5 -0.5 -0.5 -0.5 -0.5 -0.5 -65 -65 Max. 4.5 4.5 6 6 6 6 150 125 Units V V V V V V
o o
C
C
Recommended Operating Conditions
Symbol VCCD, VCCA VCCJ VIN VMON VMONGS VOUT TAPROG TA Parameter Core supply voltage at pin JTAG logic supply voltage at pin Input voltage at digital input pins Input voltage at VMON pins Input voltage at VMONGS pins Open-drain output voltage Ambient temperature during programming Ambient temperature Power applied CLTLOCK/SMBA Conditions Min. 2.8 2.25 -0.3 -0.3 -0.3 -0.3 -40 -40 Max. 3.96 3.6 5.5 5.9 0.3 5.5 85 85 Units V V V V V V
o o
C
C
Analog Specifications
Symbol ICC
1
Parameter Supply current Supply current
Conditions
Min.
Typ.
Max. 10 1
Units mA mA
ICCJ
1. Includes currents on VCCD and VCCA supplies.
Analog Voltage Monitor Inputs (VMON)
Symbol RIN CIN Parameter Input resistance Input capacitance Conditions Input mode = Attenuated1 Input mode = Unattenuated Min. 50 Typ. 65 10 12 Max. 80 Units k M pF
1. True for Vmon input voltage from 600mV to 2.048V. Values less than 600mV will see higher input impedance values.
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Lattice Semiconductor
ispPAC-POWR6AT6 Data Sheet
Margin/Trim DAC Output Characteristics
Symbol Resolution FSR LSB IOUT Full scale range LSB step size Output source/sink current Offset 1 VBPZ Bipolar zero output voltage (code=80h) Offset 2 Offset 3 Offset 4 DAC code changed from 80H to FFH or 80H to 00H Single DAC code change 256 50
2
Parameter
Conditions
Min
Typ 8(7+sign) +/-320 2.5
Max
Units bits mV mV
-125 0.6 0.8 1.0 1.25
125
A
V
TS
TrimCell output voltage settling time1
2.5
ms s pF s
C_LOAD TUPDATEM TOSE
Maximum load capacitance Update time through I C port
2
260 Full scale DAC corresponds to 5% supply voltage variation -0.75 +0.75
Total open loop supply voltage error3
%
1. To 1% of set value with 50pf load connected to trim pins. 2. Total time required to update a single TRIMx output value by setting the associated DAC through the I 2C port. 3. This is the total resultant error in the trimmed power supply output voltage referred to any DAC code due to the DAC's INL, DNL, gain, output impedance, offset error and bipolar offset error across the industrial temperature range and the ispPAC-POWR6AT6 operating V CCA and VCCD ranges.
ADC Characteristics
Symbol Parameter ADC resolution VIN TCONVERT Input range full scale Conversion complete time Programmable attenuator = 1 Programmable attenuator = 3 Time from I2C request to complete one conversion cycle Programmable attenuator = 1 Programmable attenuator = 3 Programmable attenuator = 3 2 6 +/- 0.1 0 0 Conditions Min. Typ. 10 2.048 5.751 2002 Max. Units Bits V V s mV mV %
ADC Step Size LSB Eattenuator Error due to attenuator
1. Maximum voltage is limited by VMONX pin (theoretical maximum is 6.144V). 2. Minimum time to wait for valid ADC result. Applies when not reading the DONE status bit (via I2C) to determine ADC.
ADC Error Budget Across Entire Operating Temperature Range
Symbol Parameter Conditions Measurement Range 600 mV to 2.048V, VMONxGS > -100mV, Attenuator =1 TADC Error Total Measurement Error at Any Voltage1 Measurement Range 600 mV to 2.048V, VMONxGS > -200mV, Attenuator =1 Measurement Range 0 to 2.048V, VMONxGS > -200mV, Attenuator =1
1. Total error, guaranteed by characterization, includes INL, DNL, Gain, Offset, and PSR specs of the ADC.
Min. -8
Typ. +/-4 +/-6 +/-10
Max. 8
Units mV mV mV
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Lattice Semiconductor
ispPAC-POWR6AT6 Data Sheet
Digital Specifications
Over Recommended Operating Conditions
Symbol IIL,IIH IPU VIL Parameter Input leakage, no pull-up/pull-down Input pull-up current (TMS, TDI) Voltage input, logic low1 VPS[0:1], TDI, TMS, CLTENb, 3.3V supply VPS[0:1], TDI, TMS, CLTENb, 2.5V supply
1
Conditions
Min.
Typ. 70
Max. +/-10
Units A A
0.8 V 0.7 2.0 V 1.7 0.8 V
VIH VOL
Voltage input, logic high
VPS[0:1], TDI, TMS, CLTENb, 3.3V supply VPS[0:1], TDI, TMS, CLTENb, 2.5V supply ISINK = 20mA
CLTLOCK/SMBA
1. CLTENb, VPS[0:1] referenced to VCCD; TDO, TDI, TMS referenced to VCCJ.
I2C Port Characteristics
100KHz Symbol FI2C TSU;STA THD;STA TSU;DAT TSU;STO THD;DAT TLOW THIGH TF TR TTIMEOUT TPOR TBUF I C clock/data rate After start After start Data setup Stop setup Data hold; SCL= Vih_min = 2.1V Clock low period Clock high period Fall time; 2.25V to 0.65V Rise time; 0.65V to 2.25V Detect clock low timeout Device must be operational after power-on reset Bus free time between stop and start condition 25 500 4.7 4.7 4 250 4 0.3 4.7 4 300 1000 35 25 500 1.3 3.45
2
400KHz Min. 0.6 0.6 100 0.6 0.3 1.3 0.6 300 300 35 0.9 Max. 400
1
Definition
Min.
Max. 100
1
Units KHz us us ns us us us us ns ns ms ms us
1. If FI2C is less than 50kHz, then the ADC DONE status bit is not guaranteed to be set after a valid conversion request is completed. In this case, waiting for the TCONVERT minimum time after a convert request is made is the only way to guarantee a valid conversion is ready for readout. When FI2C is greater than 50kHz, ADC conversion complete is ensured by waiting for the DONE status bit.
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Lattice Semiconductor
ispPAC-POWR6AT6 Data Sheet
Timing for JTAG Operations
Symbol tISPEN tISPDIS tHVDIS tHVDIS tCEN tCDIS tSU1 tH tCKH tCKL fMAX tCO tPWV tPWP Parameter Program enable delay time Program disable delay time High voltage discharge time, program High voltage discharge time, erase Falling edge of TCK to TDO active Falling edge of TCK to TDO disable Setup time Hold time TCK clock pulse width, high TCK clock pulse width, low Maximum TCK clock frequency Falling edge of TCK to valid output Verify pulse width Programming pulse width Conditions Min. 10 30 30 200 -- -- 5 10 20 20 -- -- 30 20 Typ. -- -- -- -- -- -- -- -- -- -- -- -- -- -- Max. -- -- -- -- 10 10 -- -- -- -- 25 10 -- -- Units s s s s ns ns ns ns ns ns MHz ns s ms
Figure 2. Erase (User Erase or Erase All) Timing Diagram
VIH
TMS
VIL
tSU1
VIH
tH tCKH
tSU1 tGKL
tH
tSU1
Clock to Shift-IR state and shift in the Discharge Instruction, then clock to the Run-Test/Idle state
tH tCKH
tSU1
tH tCKH
tSU1 tGKL
tH tCKH
tSU1
tH tCKH
TCK
VIL
tSU2
Specified by the Data Sheet
State
Update-IR
Run-Test/Idle (Erase)
Select-DR Scan
Run-Test/Idle (Discharge)
Figure 3. Programming Timing Diagram
VIH
TMS
VIL
tSU1
VIH
tH tCKH
tSU1 tCKL
tH tPWP
tSU1
tH tCKH
Clock to Shift-IR state and shift in the next Instruction, which will stop the discharge process
tSU1
tH tCKH
tSU1 tCKL
tH tCKH
TCK
VIL
State
Update-IR
Run-Test/Idle (Program)
Select-DR Scan
Update-IR
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Lattice Semiconductor
Figure 4. Verify Timing Diagram
VIH
ispPAC-POWR6AT6 Data Sheet
TMS
VIL
tSU1
VIH
tH tCKH
tSU1 tCKL
tH tPWV
tSU1
tH tCKH
Clock to Shift-IR state and shift in the next Instruction
tSU1
tH tCKH
tSU1 tCKL
tH tCKH
TCK
VIL
State
Update-IR
Run-Test/Idle (Program)
Select-DR Scan
Update-IR
Figure 5. Discharge Timing Diagram
VIH
tHVDIS (Actual)
Clock to Shift-IR state and shift in the Verify Instruction, then clock to the Run-Test/Idle state
TMS
VIL
tSU1
VIH
tH tCKH
tSU1 tCKL
tH tPWP
tSU1
tH tCKH
tSU1
tH tCKH
tSU1 tCKL
tH tCKH
tSU1 tPWV
Actual
tH tCKH
TCK
VIL
tPWV
Specified by the Data Sheet
State
Update-IR
Run-Test/Idle (Erase or Program)
Select-DR Scan
Run-Test/Idle (Verify)
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Lattice Semiconductor
ispPAC-POWR6AT6 Data Sheet
Theory of Operation
Voltage Measurement with the On-chip Analog to Digital Converter (ADC)
The ispPAC-POWR6AT6 has an on-chip analog to digital converter that can be used for measuring the voltages at the VMON inputs. The ADC is also used in closed loop trimming of DC-DC converters. Close loop trimming is covered later in this document. Figure 6. ADC Monitoring VMON1 to VMON6
Programmable Attenuator
VMON 1
+ -
/3 / /1
VMON 2
+ -
/3 / /1 To Closed Loop Trim Circuit /3 / /1 ADC MUX ADC
VMON 3
+ -
10
To I2C Readout Register
VMON 4
+ -
/3 / /1
VMON 5
+ -
/3 / /1
Internal VREF2.048V
VMON 6
+ -
/3 / /1
3
From Closed Loop Trim Circuit
From I2C ADC MUX Address
Figure 6 shows the ADC circuit arrangement within the ispPAC-POWR6AT6 device. The ADC can measure all analog input voltages through the multiplexer, ADC MUX. The programmable attenuator between the ADC mux and VMON pins can be configured as divided-by-3 or divided-by-1 (no attenuation). The divided-by-3 setting is used to measure voltages from 0V to 6V range and divided-by-1 setting is used to measure the voltages from 0V to 2V range. A microcontroller can place a request for any VMON voltage measurement at any time through the I2C bus. Upon the receipt of an I2C command, the ADC will be connected to the I2C selected VMON through the ADC MUX. The ADC output is then latched into the I2C readout registers.
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Lattice Semiconductor
ispPAC-POWR6AT6 Data Sheet
Calculation The algorithm to convert the ADC code to the corresponding voltage takes into consideration the attenuation bit value. In other words, if the attenuation bit is set, then ADC output logic multiplies the 10-bit ADC code by 3 to calculate the actual voltage at that VMON input. The following formula can always be used to calculate the actual voltage from the ADC code. Voltage at the VMONx Pins VMONx = ADC code (12 bits1, converted to decimal) * 2mV
1
Note: ADC_VALUE_HIGH (8 bits), ADC_VALUE_LOW (4 bits) read from I2C/SMBUS interface
Controlling Power Supply Output Voltage with the Margin/ Trim Block
One of the key features of the ispPAC-POWR6AT6 is its ability to make adjustments to the power supplies that it may also be monitoring. This is accomplished through the Trim and Margin Block of the device. The Trim and Margin Block can adjust voltages of up to six different power supplies through TrimCells as shown in Figure 7. The DCDC blocks in the figure represent virtually any type of DC power supply that has a trim or voltage adjustment input. This can be an off-the-shelf unit or custom circuit designed around a switching regulator IC. The interface between the ispPAC-POWR6AT6 and the DC power supply is represented by a single resistor (R1 to R6) to simplify the diagram. Each of these resistors represents a resistor network. Other control signals driving the Margin/Trim Block are: * VPS [1:0] - Control signals from device pins common to all six TrimCells, which are used to select the active voltage profile for all TrimCells together. * ADC input - Used to determine the trimmed DC-DC converter voltage. * CLTENb - Used to enable closed loop trimming of all TrimCells together. Next to each DC-DC converter, four voltages are shown. These voltages correspond to the operating voltage profile of the Margin/Trim Block. When the VPS[1:0] = 00, representing Voltage Profile 0: (Voltage Profile 0 is recommended to be used for the normal circuit operation) The output voltage of the DC-DC converter controlled by the Trim 1 pin of the ispPAC-POWR6AT6 will be 1V and that TrimCell is operating in closed loop trim mode. At the same time, the DC-DC converters controlled by Trim 2, Trim 3 and Trim 6 pins output 1.2V, 1.5V and 3.3V respectively. When the VPS[1:0] = 01, representing Voltage Profile 1 being active: The DC-DC output voltage controlled by Trim 1, 2, 3, and 6 pins will be 1.05V, 1.26V, 1.57V, and 3.46V. These supply voltages correspond to 5% above their respective normal operating voltage (also called as margin high). Similarly, when VPS[1:0] = 11, all DC-DC converters are margined low by 5%.
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Lattice Semiconductor
Figure 7. ispPAC-POWR6AT6 Trim and Margin Block
ispPAC-POWR6AT6 Margin/Trim Block
ispPAC-POWR6AT6 Data Sheet
VIN
DC-DC
Trim-in
DC-DC Output Voltage Controlled by Profiles 0 1 1V (CLT) 1.05V 2 0.97V 3 0.95V
TrimCell #1
(Closed Loop)
Trim 1
R1*
CLTENb TrimCell #2
(I2C Update) Trim 2 R2*
VIN
1.2V (I2C) 1.26V 1.16V 1.14V
DC-DC
Trim-in
Digital Closed Loop and I2C Interface Control
VIN
1.5V (I2C) 1.57V 1.45V 1.42V
VPS[0:1]
TrimCell #3
(I2C Update)
Trim 3
R3*
DC-DC
Trim-in
VIN
3.3V (EE) 3.46V 3.20V 3.13V
CLTLOCK/SMBA
TrimCell #6
(Register 0)
Trim 6
R6*
DC-DC
Trim-in
*Indicates resistor network (see Figure 8).
Input From ADC Mux Read - 10-bit ADC Code
There are six TrimCells in the ispPAC-POWR6AT6 device, enabling simultaneous control of up to six individual power supplies. Each TrimCell can generate up to four trimming voltages to control the output voltage of the DC-DC converter. Figure 8. TrimCell Driving a Typical DC-DC Converter
VOUT
VIN VOUT R3 TrimCell #N DAC R1 R2 Trim DC-DC Converter
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Lattice Semiconductor
ispPAC-POWR6AT6 Data Sheet
Figure 8 shows the resistor network between the TrimCell #N in the ispPAC-POWR6AT6 and the DC-DC converter. The values of these resistors depend on the type of DC-DC converter used and its operating voltage range. The method to calculate the values of the resistors R1, R2, and R3 are described in a separate application note. Voltage Profile Control The Margin / Trim Block of ispPAC-POWR6AT6 consists of six TrimCells. Because all six TrimCells in the Margin / Trim Block are controlled by a common voltage profile control signals, they all operate at the same voltage profile. The voltage profile control input comes from a pair of device pins: VPS0, VPS1. TrimCell Architecture The TrimCell block diagram is shown in Figure 9. The 8-bit DAC at the output provides the trimming voltage required to set the output voltage of a programmable supply. Each TrimCell can be operated in any one of the four voltage profiles. In each voltage profile the output trimming voltage can be set to a preset value. There are six 8-bit registers in each TrimCell that, depending on the operational mode, set the DAC value. Of these, four DAC values (DAC Register 0 to DAC Register 3) are stored in the E2CMOS memory while the remaining register contents are stored in volatile registers. Two multiplexers (Mode Mux and Profile Mux) control the routing of the code to the DAC. The Profile Mux can be controlled by common TrimCell voltage profile control signals. Figure 9. ispPAC-POWR6AT6 Output TrimCell
TRIMCELL ARCHITECTURE
VOLTAGE PROFILE 3 VOLTAGE PROFILE 2 VOLTAGE PROFILE 1 DAC REGISTER 3 (E2CMOS) DAC REGISTER 2 (E2CMOS) DAC REGISTER 1 (E2CMOS) DAC REGISTER 0 (E2CMOS) VOLTAGE PROFILE 0 DAC REGISTER (I2C) CLOSED LOOP TRIM REGISTER 8 VOLTAGE PROFILE 0 MODE SELECT (E2CMOS) 8 8
8
11
PROFILE MUX
8
10 01 00
8
DAC
TRIMx
8 2
8
MODE MUX
COMMON TrimCell VOLTAGE PROFILE CONTROL
FROM CLOSED LOOP TRIM CIRCUIT
Figure 7 shows four power supply voltages next to each DC-DC converter. When the Profile MUX is set to Voltage Profile 3, the DC supply controlled by Trim 1 will be at 0.95V, the DC supply controlled by Trim 2 will be at 1.14V, 1.42V for Trim 3 and 3.13V for Trim 8. When Voltage Profile 0 is selected, Trim 1 will set the supply to 1V, Trim 2 and Trim 3 will be set by the values that have been loaded using I2C at 1.2 and 1.5V, and Trim 6 will be set to 3.3V. The following table summarizes the voltage profile selection and the corresponding DAC output trimming voltage. The voltage profile selection is common to all six TrimCells.
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Lattice Semiconductor
Table 1. TrimCell Voltage Profile and Operating Modes
VPS[1:0] 11 10 01 00 Selected Voltage Profile Voltage Profile 3 Voltage Profile 2 Voltage Profile 1 Voltage Profile 0 Selected Mode -- -- -- DAC Register 0 Select
ispPAC-POWR6AT6 Data Sheet
Trimming Voltage is Controlled by DAC Register 3 (E2CMOS) DAC Register 2 (E2CMOS) DAC Register 1 (E2CMOS) DAC Register 0 (E2CMOS) DAC Register (I2C) Closed Loop Trim Register
DAC Register I C Select Digital Closed Loop Trim
2
TrimCell Operation in Voltage Profiles 1, 2 and 3: The output trimming voltage is determined by the code stored in the DAC Registers 1, 2, and 3 corresponding to the selected Voltage Profile. TrimCell Operation in Voltage Profile 0: The Voltage Profile 0 has three operating modes. They are DAC Register 0 Select mode, DAC Register I2C Select mode and Closed Loop Trim mode. The mode selection is stored in the E2CMOS configuration memory. Each of the six TrimCells can be independently set to different operating modes during Voltage Profile 0 mode of operation. DAC Register 0 Select Mode: The contents of DAC register 0 are stored in the on-chip E2CMOS memory. When Voltage Profile 0 is selected, the DAC will be loaded with the value stored in DAC Register 0. DAC Register I2C Select Mode: This mode is used if the power management arrangement requires an external microcontroller to control the DC-DC converter output voltage. The microcontroller updates the contents of the DAC Register I2C on the fly to set the trimming voltage to a desired value. The DAC Register I2C is a volatile register and is reset to 80H (DAC at Bipolar zero) upon power-on. The external microcontroller writes the correct DAC code in this DAC Register I2C before enabling the programmable power supply. Digital Closed Loop Trim Mode Closed loop trim mode operation can be used when tight control over the DC-DC converter output voltage at a desired value is required. The closed loop trim mechanism operates by comparing the measured output voltage of the DC-DC converter with the internally stored voltage setpoint. The difference between the setpoint and the actual DC-DC converter voltage generates an error voltage. This error voltage adjusts the DC-DC converter output voltage toward the setpoint. This operation iterates until the setpoint and the DC-DC converter voltage are equal. Figure 10 shows the closed loop trim operation of a TrimCell. At regular intervals (as determined by the Update Rate Control register) the ispPAC-POWR6AT6 device initiates the closed loop power supply voltage correction cycle through the following blocks: * Non-volatile Setpoint register stores the desired output voltage * On-chip ADC is used to measure the voltage of the DC-DC converter * Three-state comparator is used to compare the measured voltage from the ADC with the Setpoint register contents. The output of the three state comparator can be one of the following: * +1 if the setpoint voltage is greater than the DC-DC converter voltage * -1 if the setpoint voltage is less than the DC-DC converter voltage * 0 if the setpoint voltage is equal to the DC-DC converter voltage * Channel polarity control determines the polarity of the error signal * Closed loop trim register is used to compute and store the DAC code corresponding to the error voltage. The contents of the Closed Loop Trim will be incremented or decremented depending on the channel polarity and the three-state comparator output. If the three-state comparator output is 0, the closed loop trim register contents are left unchanged. * The DAC in the TrimCell is used to generate the analog error voltage that adjusts the attached DC-DC converter output voltage.
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Lattice Semiconductor
Figure 10. Digital Closed Loop Trim Operation
ispPAC-POWR6AT6 Data Sheet
SETPOINT (E2CMOS) CHANNEL POLARITY (E2CMOS)
E2CMOS Registers DAC Register 3 DAC Register 2 DAC Register 1 DAC Register 0
TrimCell TRIMx
DAC
Three-State DIGITAL COMPARE (+1/0/-1)
+/-1
DAC Register I2C Closed Loop Trim Register
Profile Control
R* TRIMIN
UPDATE RATE CONTROL
Profile 0 Mode Control (E2CMOS)
VMONx ADC
DC-DC CONVERTER
VOUT GND
POWR6AT6
E2CMOS
*Indicates resistor network (see Figure 8).
The closed loop trim cycle interval is programmable and is set by the update rate control register. The following table lists the programmable update interval that can be selected by the update rate register. Table 2. Output DAC Update Rate in Digital Closed Loop Mode
Update Rate Control Value 00 01 10 11 Update Interval 432 s 1.06 ms 8.74 ms 16.9 ms
Closed Loop Trim Control Using the CLTENb Pin There is a one-to-one relationship between the selected TrimCell and the corresponding VMON input for the closed loop operation. For example, if TrimCell 3 is used to control the power supply in the closed loop trim mode, VMON3 must be used to monitor its output power supply voltage. The CLTENb enable pin (active low) simultaneously starts the closed loop trimming process for all ispPACPOWR6AT6 trim outputs so configured. Behavior of individual trim output pins is defined using Lattice PACDesigner design software and stored in the ispPAC-POWR6AT6's non-volatile E2CMOS memory. In addition to a closed-loop trim control option, two other configuration alternatives are available. The first stores a fixed, or static, value for a given trim output in E2CMOS memory. The second enables dynamic trim adjustments to be made using an external microcontroller via the ispPAC-POWR6AT6's I2C interface bus. Neither of these options is affected by the CLTENb pin, however. When the ispPAC-POWR6AT6's CLTENb pin goes low, closed-loop trimming is enabled. When CLTENb subsequently goes high, there is a brief delay after which closed-loop trimming is suspended. The delay is the time required for ispPAC-POWR6AT6 control logic to complete a trim update cycle. Table 2 shows typical times for update cycles based on which of four trim rates is initially chosen in PAC-Designer. When the trim process is halted, it should also be noted the trim output DACs have constant voltage output levels (corresponding to their last input code setting). This condition can be safely maintained indefinitely, but resuming closed-loop trimming (by taking CLTENb low) better insures power supplies remain precisely adjusted under all possible conditions. When reenabled, closed-loop trimming restarts where it left off. In this sense, the CLTENb pin can be thought of as a "pause" control for closed-loop trim.
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Lattice Semiconductor
ispPAC-POWR6AT6 Data Sheet
It should also be noted that whenever the VPS0 and VPS1 pins are not both low, they effectively stop closed-loop trim the same way the CLTENb pin does when it goes high. That is, whenever an alternate trim mode (other than VPS0=0 and VPS1=0) is selected, the trim process is suspended as described above. Assuming the CLTENb pin is asserted, when both VPS0 and VPS1 are low again, closed-loop trimming will resume where it left off. It is recommended that the CLTENb pin not be activated until after any necessary power supply sequencing is completed to prevent an "open loop" condition from occurring. Otherwise, if control of when closed-loop trimming begins is not critical, the CLTENb pin can be tied to ground. This will cause closed-loop trim to begin immediately after the initial power on of the ispPAC-POWR6AT6 is completed. Closed Loop Trim Start-up Behavior The contents of the closed loop register, upon power-up, will contain a value 80h (Bipolar-zero) value. The DAC output voltage will be equal to the programmed Offset voltage. Usually under this condition, the power supply output will be close to its nominal voltage. If the power supply trimming should start after reaching its desired output voltage, the corresponding DAC code can be loaded into the closed loop trim register through I2C (same address as the DAC register I2C mode) before activating the CLTENb pin.
Details of the Digital to Analog Converter (DAC)
Each TrimCell has an 8-bit bipolar DAC to set the trimming voltage (Figure 11). The full-scale output voltage of the DAC is +/- 320 mV. A code of 80H results in the DAC output set at its bi-polar zero value. The voltage output from the DAC is added to a programmable offset value and the resultant voltage is then applied to the trim output pin. The offset voltage is typically selected to be approximately equal to the DC-DC converter open circuit trim node voltage. This results in maximizing the DC-DC converter output voltage range. The programmed offset value can be set to 0.6V, 0.8V, 1.0V or 1.25V. This value selection is stored in E2CMOS memory and cannot be changed dynamically. Figure 11. Vbpz Offset Voltage is Added to DAC Output Voltage to Derive Trim Pad Voltage
TrimCell X
8 From Trim Registers
DAC 7 bits + Sign (-320mV to +320mV)
TRIMx Pad
Vbpz Offset (0.6V,0.8V,1.0V,1.25V) E2CMOS
RESET Command via JTAG or I2C
Issuing a reset instruction via JTAG or I2C will force all trim outputs selected for digital closed-loop trim control back to their initial output level (code 80h + Vbpz). After that, assuming the CLTENb is still asserted, digital closed loop
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Lattice Semiconductor
ispPAC-POWR6AT6 Data Sheet
trim will begin and CLTLOCK/SMBA will only reassert when the trim process is complete. Contents of the I2C cltlock_status register (0x00), however are not fully reset to initial conditions until the CLTLOCK/SMBA pin achieves a reasserted state. CAUTION: Issuing a RESET command through I 2C or JTAG during the ispPAC-POWR6AT6 device operation, results in the device aborting all operations and returning to the power-on reset state except for the one condition mentioned above.
I2C/SMBUS Interface
I2C and SMBus are low-speed serial interface protocols designed to enable communications among a number of devices on a circuit board. The ispPAC-POWR6AT6 supports a 7-bit addressing of the I2C communications protocol, as well as SMBTimeout and SMBAlert features of the SMBus, enabling it to easily integrated into many types of modern power management systems. Figure 12 shows a typical I2C configuration, in which one or more ispPACPOWR6AT6s are slaved to a supervisory microcontroller. SDA is used to carry data signals, while SCL provides a synchronous clock signal. The SMBAlert line is only present in SMBus systems. The 7-bit I2C address of the POWR6AT6 is fully programmable through the JTAG port. Figure 12. ispPAC-POWR6AT6 in I 2C/SMBUS System
V+
SDA/SMDAT (DATA) SCL/SMCLK (CLOCK) SMBALERT To Other I2C Devices
SDA
SCL
INTERRUPT
SDA
SCL
OUT5/ SMBA
SDA
SCL
OUT5/ SMBA
MICROPROCESSOR (I2C MASTER)
ispPAC-POWR6AT6 (I2C SLAVE)
ispPAC-POWR6AT6 (I2C SLAVE)
In both the I2C and SMBus protocols, the bus is controlled by a single MASTER device at any given time. This master device generates the SCL clock signal and coordinates all data transfers to and from a number of slave devices. The ispPAC-POWR6AT6 is configured as a slave device, and cannot independently coordinate data transfers. Each slave device on a given I2C bus is assigned a unique address. The ispPAC-POWR6AT6 implements the 7-bit addressing portion of the standard. Any 7-bit address can be assigned to the ispPAC-POWR6AT6 device by programming through JTAG. When selecting a device address, one should note that several addresses are reserved by the I2C and/or SMBus standards, and should not be assigned to ispPAC-POWR6AT6 devices to assure bus compatibility. Table 3 lists these reserved addresses.
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Lattice Semiconductor
Table 3. I 2C/SMBus Reserved Slave Device Addresses
Address 0000 000 0000 000 0000 001 0000 010 0000 011 0000 1xx 0001 000 0001 100 0101 000 0110 111 1100 001 1111 0xx 1111 1xx R/W bit 0 1 x x x x x x x x x x x I2C function Description General Call Address Start Byte CBUS Address Reserved Reserved HS-mode master code NA NA NA NA NA 10-bit addressing Reserved
ispPAC-POWR6AT6 Data Sheet
SMBus Function General Call Address Start Byte CBUS Address Reserved Reserved HS-mode master code SMBus Host SMBus Alert Response Address Reserved for ACCESS.bus Reserved for ACCESS.bus SMBus Device Default Address 10-bit addressing Reserved
The ispPAC-POWR6AT6's I2C/SMBus interface allows data to be both written to and read from the device. A data write transaction (Figure 13) consists of the following operations: 1. Start the bus transaction 2. Transmit the device address (7 bits) along with a low write bit 3. Transmit the address of the register to be written to (8 bits) 4. Transmit the data to be written (8 bits) 5. Stop the bus transaction To start the transaction, the master device holds the SCL line high while pulling SDA low. Address and data bits are then transferred on each successive SCL pulse, in three consecutive byte frames of 9 SCL pulses. Address and data are transferred on the first 8 SCL clocks in each frame, while an acknowledge signal is asserted by the slave device on the 9th clock in each frame. Both data and addresses are transferred in a most-significant-bit-first format. The first frame contains the 7-bit device address, with bit 8 held low to indicate a write operation. The second frame contains the register address to which data will be written, and the final frame contains the actual data to be written. Note that the SDA signal is only allowed to change when the SCL is low, as raising SDA when SCL is high signals the end of the transaction. Figure 13. I 2C Write Operation
SCL SDA
START 1 A6 2 A5 3 A4 4 A3 5 A2 6 A1 7 A0 8 R/W 9 ACK 1 R7 2 R6 3 R5 4 R4 5 R3 6 R2 7 R1 8 R0 9 ACK 1 D7 2 D6 3 D5 4 D4 5 D3 6 D2 7 D1 8 D0 9 ACK
DEVICE ADDRESS (7 BITS)
REGISTER ADDRESS (8 BITS)
WRITE DATA (8 BITS)
STOP
Note: Shaded Bits Asserted by Slave
Reading a data byte from the ispPAC-POWR6AT6 requires two separate bus transactions (Figure 14). The first transaction writes the register address from which a data byte is to be read. Note that since no data is being written to the device, the transaction is concluded after the second byte frame. The second transaction performs the actual read. The first frame contains the 7-bit device address with the R/W bit held High. In the second frame the ispPACPOWR6AT6 asserts data out on the bus in response to the SCL signal. Note that the acknowledge signal in the second frame is asserted by the master device and not the ispPAC-POWR6AT6.
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Lattice Semiconductor
Figure 14. I 2C Read Operation
STEP 1: WRITE REGISTER ADDRESS FOR READ OPERATION SCL SDA
START
ispPAC-POWR6AT6 Data Sheet
1 A6
2 A5
3 A4
4 A3
5 A2
6 A1
7 A0
8 R/W
9 ACK
1 R7
2 R6
3 R5
4 R4
5 R3
6 R2
7 R1
8 R0
9 ACK
DEVICE ADDRESS (7 BITS)
REGISTER ADDRESS (8 BITS)
STOP
STEP 2: READ DATA FROM THAT REGISTER
SCL SDA
START
1 A6
2 A5
3 A4
4 A3
5 A2
6 A1
7 A0
8 R/W
9 ACK
1 D7
2 D6
3 D5
4 D4
5 D3
6 D2
7 D1
8 D0
9 ACK
DEVICE ADDRESS (7 BITS)
READ DATA (8 BITS)
OPTIONAL
STOP
Note: Shaded Bits Asserted by Slave
The ispPAC-POWR6AT6 provides 15 registers that can be accessed through its I2C interface. These registers provide the user with the ability to monitor and control the device's inputs and outputs, and transfer data to and from the device. Table 4 provides a summary of these registers. Table 4. I 2C Control Registers
Register Address 0x00 0x01 0x02 0x03 0x04 0x05 0x06 0x07 0x08 0x09 0x0A 0x0B 0x0C 0x0D 0x0E Register Name cltlock_status adc_value_low adc_value_high adc_mux UES_byte0 UES_byte1 UES_byte2 UES_byte3 reset trim1_trim trim2_trim trim3_trim trim4_trim trim5_trim trim6_trim Read/Write R/W R R R/W R R R R W R/W R/W R/W R/W R/W R/W Description Closed-loop trim status *bit-6 is RW, all others R only ADC D[3:0] and status ADC D[11:4] ADC Attenuator and MUX[3:0] UES[7:0] UES[15:8] UES[23:16] UES[31:24] Resets device on write Trim DAC 1 [7:0] Trim DAC 2 [7:0] Trim DAC 3 [7:0] Trim DAC 4 [7:0] Trim DAC 5 [7:0] Trim DAC 6 [7:0] Value on POR, RESET 1100 0000 0000 1110 0000 0000 1110 1000 EEEE EEEE EEEE EEEE EEEE EEEE EEEE EEEE 1111 1111 1000 0000 1000 0000 1000 0000 1000 0000 1000 0000 1000 0000
Note: x = unknown, 0 = low, 1 = high, E= E2 memory setting (UES string)
I2C Closed-Loop Trim Register
Figure 15 shows bit assignments for the ispPAC-POWR6AT6 I2C closed-loop trim status register. There are six read only bits (cltlock_status.in[1:6]) that reflect the present trim status of individual trim output pins. When a closed loop-trim controlled power supply's output reaches the value specified by its Profile 0 configuration setting, that trim output's CLTLOCK_status bit is set to a "1". The I2C closed-loop trim register has one read/write bit (cltlock_status). When ispPAC-POWR6AT6 is configured in PAC-Designer to operate in SMBus Alert mode, it is set to a "1" by device control logic to send an SMBus Alert. Logic then waits for it to be acknowledged by a host I2C processor (when it is addresses the register), completing 19
Lattice Semiconductor
ispPAC-POWR6AT6 Data Sheet
the SMBus Alert cycle. Refer to the CLTLOCK/SMBA pin and SMBus Alert sections of this datasheet for more information on how the closed-loop trim status in this I2C register is used. Figure 15. I2C Closed Loop Trim Status Register
0x00 - CLTLOCK_STATUS (b6 = Read/Write; all others Read Only)
X b7 SMBA b6 in6 b5 in5 b4 in4 b3 in3 b2 in2 b1 in1 b0
It is possible to read the value of the voltage present on any of the VMON inputs by using the ispPAC-POWR6AT6's ADC. Three registers provide the I2C interface to the ADC (Figure 16). Figure 16. ADC Interface Registers
0x01 - ADC_VALUE_LOW (Read Only)
D3 b7 D2 b6 D1 b5 D0 b4 1 b3 1 b2 1 b1 DONE b0
0x02 - ADC_VALUE_HIGH (Read Only)
D11 b7 D10 b6 D9 b5 D8 b4 D7 b3 D6 b2 D5 b1 D4 b0
0x03 - ADC_MUX (Read/Write)
X b7 X b6 X b5 ATTEN b4 X b3 SEL2 b2 SEL1 b1 SEL0 b0
To perform an A/D conversion, one must set the input attenuator and channel selector. Two input ranges may be set using the attenuator, 0 - 2.048V and 0 - 6.144V. Table 5 shows the input attenuator settings. Table 5. ADC Input Attenuator Control
ATTEN (ADC_MUX.4) 0 1 Resolution 2mV 6mV Full-Scale Range 2.048 V 6.144 V
The input selector may be set to monitor any one of the six VMON inputs or the VCCA input. Table 6 shows the codes associated with each input selection. Table 6. VMON Address Selection Table
Select Word SEL2 (ADC_MUX.2) 0 0 0 0 1 1 SEL1 (ADC_MUX.1) 0 0 1 1 0 0 SEL0 (ADC_MUX.0) 0 1 0 1 0 1 Input Channel VMON1 VMON2 VMON3 VMON4 VMON5 VMON6
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Lattice Semiconductor
ispPAC-POWR6AT6 Data Sheet
Writing a value to the ADC_MUX register to set the input attenuator and selector will automatically initiate a conversion. When the conversion is in process, the DONE bit (ADC_VALUE_LOW.0) will be reset to 0. When the conversion is complete, this bit will be set to 1. When the conversion is complete, the result may be read out of the ADC by performing two I2C read operations; one for ADC_VALUE_LOW, and one for ADC_VALUE_HIGH. It is recommended that the I2C master load a second conversion command only after the completion of the current conversion command (Waiting for the DONE bit to be set to 1). An alternative would be to wait for a minimum specified time (see Tconvert value in the specifications) and disregard checking the DONE bit. Note that if the I2C clock rate falls below 50kHz (see FI2C note in specifications), the only way to insure a valid ADC conversion is to wait the minimum specified time (Tconvert), as the operation of the DONE bit at clock rates lower than that cannot be guaranteed. In other words, if the I2C clock rate is less than 50kHz, the DONE bit may or may not assert even when a valid conversion result is available. Erroneous ADC readout results are also possible whenever the I2C clock is less than 50kHz and a second ADC convert is commanded before a full TCONVERT time period has elapsed. Under these conditions, it is still possible to obtain valid results for the second conversion by reading out the ADC low and high byte results twice in succession (read ADC_VALUE_LOW, read ADC_VALUE_HIGH, then repeating the low and high byte reads). Only the second ADC readout value is reliably valid, however. To insure every ADC conversion result is valid, preferred operation is to clock I2C at more than 50kHz and verify DONE bit status or wait for the full TCONVERT time period between subsequent ADC convert commands. If an I2C request is placed before the current conversion is complete, the DONE bit will be set to 1 only after the second request is complete. The UES word may also be read through the I2C interface, with the register mapping shown in Figure 17. Figure 17. I 2C Register Mapping for UES Bits
0x04 - UES_BYTE0 (Read Only)
UES7 b7 UES6 b6 UES5 b5 UES4 b4 UES3 b3 UES2 b2 UES1 b1 UES0 b0
0x05 - UES_BYTE1 (Read Only)
UES15 b7 UES14 b6 UES13 b5 UES12 b4 UES11 b3 UES10 b2 UES9 b1 UES8 b0
0x06 - UES_BYTE2 (Read Only)
UES23 b7 UES22 b6 UES21 b5 UES20 b4 UES19 b3 UES18 b2 UES17 b1 UES16 b0
0x07 - UES_BYTE3 (Read Only)
UES31 b7 UES30 b6 UES29 b5 UES28 b4 UES27 b3 UES26 b2 UES25 b1 UES24 b0
The I2C interface also provides the ability to initiate reset operations. The ispPAC-POWR6AT6 may be reset by issuing a write of any value to the I2C RESET register (Figure 18). Refer to the RESET Command via JTAG or I2C section of this data sheet for further information.
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Lattice Semiconductor
Figure 18. I 2C Reset Register
0x8 - RESET (Write Only)
X b7 X b6 X b5 X b4 X b3 X b2
ispPAC-POWR6AT6 Data Sheet
X b1
X b0
The ispPAC-POWR6AT6 also provides the user with the ability to program the trim values over the I2C interface, by writing the appropriate binary word to the associated trim register (Figure 19). Figure 19. I 2C Trim Registers
0x9 - TRIM1_TRIM (Read/Write)
D7 b7 D6 b6 D5 b5 D4 b4 D3 b3 D2 b2 D1 b1 D0 b0
0xA - TRIM2_TRIM (Read/Write)
D7 b7 D6 b6 D5 b5 D4 b4 D3 b3 D2 b2 D1 b1 D0 b0
0xB - TRIM3_TRIM (Read/Write)
D7 b7 D6 b6 D5 b5 D4 b4 D3 b3 D2 b2 D1 b1 D0 b0
0xC - TRIM4_TRIM (Read/Write)
D7 b7 D6 b6 D5 b5 D4 b4 D3 b3 D2 b2 D1 b1 D0 b0
0xD - TRIM5_TRIM (Read/Write)
D7 b7 D6 b6 D5 b5 D4 b4 D3 b3 D2 b2 D1 b1 D0 b0
0xE - TRIM6_TRIM (Read/Write)
D7 b7 D6 b6 D5 b5 D4 b4 D3 b3 D2 b2 D1 b1 D0 b0
Monitoring Closed Loop Trim with the CLTLOCK/SMBA Pin
The ispPAC-POWR6AT6 uses a simple algorithm to determine if closed-loop trimming has reached a stable or locked value. In Figure 20, the flow diagram shows whenever the closed-loop trim enable pin (CLTENb) is asserted (low) the status of all six trim output pins is tested and updated at periodic intervals (refer to Table 2 for typical cycle times). If a trim lock condition exists for a given pin, a lock result is set and processing continues. Pins not selected for closed-loop trim are automatically reported to be in the lock condition, but timing is kept constant to preserve a constant update rate regardless of how many trim outputs are really involved.
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ispPAC-POWR6AT6 Data Sheet
Figure 20. Closed-Loop Trim Lock (CLTLOCK/SMBA) Signal Processing Logic Flow Diagram
Start Runs when CLTENb pin is asserted.
Vmon-n ADC measurement Yes
Determine "Lock" status of Trim-n
Trim Locked?
Set "Lock" result for Trim-n
No
Clear "Lock" result for Trim-n
The ispPAC-POWR6AT6 contains trim detection processing circuitry to signal when closed-loop trimming is complete for selected trim output pins. This signal is output on the closed-loop control output pin (CLTLOCK/SMBA) which has a open drain output and is normally asserted low (pull down). When all closed-loop trim output pins reach a completion or trim "locked" condition, the CLTLOCK/SMBA output pin pulls low. Afterwards, the CLTLOCK/ SMBA pin also indicates when a trimming fault exists by de-asserting (going high). Finally, the CLTLOCK/SMBA pin can be configured to work in conjunction with the SMBus Alert protocol to signal when trim lock has been achieved or lost (see the section on SMBus Alert for details). Figure 21 shows a simplified diagram of how the state of the CLTLOCK/SMBA output pin is generated. After closed loop trimming is enabled, the CLTLOCK/SMBA signal processing logic examines the output result from the ADC going to each TrimCell at the end of each trim update cycle. If it is determined that a trim lock condition exists for that trim output pin, the trim lock signal is asserted. The status of an individual trim output can be read via the I2C closed loop trim register (refer to Figure 15). Trim output pins not selected for closed-loop trim operation will automatically indicate a trim locked condition. Figure 21. Closed-Loop Trim Lock Output Pin (CLTLOCK/SMBA) Functionality
I 2C CLTLOCK/SMBA Status: Trim1-6 (6-bits); 1 = Locked
6 5
CLTLOCK/SMBA Signal Processing Logic
Trim1-5 same as below
5
1
0 Trim6
lock = 1
CLTLOCK/SMBA 1 I2C/ SMBus Control Logic
E 2 Configuration Mask CLTLOCK/SMBA
E 2 Configuration Default = 0
Next, an individual lock signal is OR'd with an E2CMOS mask bit specific to that trim output pin. There are six masking bits, one for each possible trim output pin. When set, masking bits effectively override the lock determination for a particular trim output pin. The default setting for all mask bits is cleared (not set). Changes to the device configuration mask bits can be made using PAC-Designer.
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Lattice Semiconductor
ispPAC-POWR6AT6 Data Sheet
Finally, the individual lock status inputs all meet at a common NAND gate. A trim lock condition is generated when all six trim status inputs are high causing the CLTLOCK/SMBA pin to go low. If the trim lock is lost for any monitored trim output pin, the CLTLOCK/SMBA pin will de-assert (go open). This could be due to a failed power supply for example, or if the ispPAC-POWR6AT6 can no longer adjust a controlled supply to specification. Interrogation of the I2C register determines which trim output pin lost lock. Also, the ADC can be used to measure individual supplies to further diagnose an underlying fault. There is an alternative path the CLTLOCK/SMBA signal can take, depending on how the ispPAC-POWR6AT6 has been configured. Refer to the I2C/SMBus control logic box shown in Figure 21. When the alternative output path is enabled in PAC-Designer, the trim lock result is first sent to the I2C/SMBus control logic for processing before going to the CLTLOCK/SMBA output pin. The purpose of this control logic is to make the CLTLOCK/SMBA signal work in accordance with the SMBus Alert protocol. The main difference between the two output path alternatives is that SMBus Alert stays set (low) until acknowledged by the host I2C processor. Also, an SMBus Alert is set (pulled low) when a trim lock condition is achieved, as well as when it is lost. Either condition must be acknowledged or the SMBus Alert condition will not go away. Note that on initial device power-on, or after an I2C software reset, an SMBus Alert is blocked (no trim lock). The SMBus master must explicitly set the CLT_LOCK_STATUS bit-6 low to begin the SMBAlert process.
SMBus SMBAlert Function
The ispPAC-POWR6AT6 provides an SMBus SMBAlert function to request service from the bus master when used as part of an SMBus system. When the SMBAlert signal mode for closed-loop trimming is chosen in PAC-Designer, the CLTLOCK/SMBA output pin will go low whenever the trim lock condition status changes. The reason for this is to report both when all outputs are in trim lock and when one or more trim output pins lose trim lock. When a selected (unmasked) closed-loop trim output loses its locked status, servicing the resulting SMBus Alert and interrogating the I2C closed-loop trim register will reveal which trim output pin(s) that are involved. After acknowledgement by the host I2C processor, the CLTLOCK/SMBA pin will be de-asserted until another change in CLTLOCK/SMBA trim status occurs. After initial device turn-on and power-on reset (POR) is complete, the SMBA bit in the I2C register (0x00, bit-6) is set high or "1". The SMBAlert function of the ispPAC-POWR6AT6 is effectively suspended until this location has been overwritten with a low or "0". The purpose of this is to prevent output to the CLTLOCK/SMBA pin before the bus master or host processor is ready to process SMBAlerts. Note that if closed loop trimming is enabled and completes before this action is performed, the initial trim lock indication (as an SMBAlert) will not occur. If this happens, trim status can still be interrogated, however. Reading the I2C trim status register to see that all trim bits are high (bit-1 to bit-6) is a valid indication that trim lock has been achieved. Otherwise, the CLTENb pin must be held high until after the I2C SMBA bit is written low and then enabled afterwards to insure detection of the initial trim lock status with an SMBAlert. After the SMBA bit has been set low, any subsequent change in trim lock status will be reported with an SMBAlert output to the CLTLOCK/SMBA pin. To process an SMBAlert, the following steps must be performed to service the alert and resume monitoring for the next change in trim lock status: The typical flow for an SMBAlert transaction is as follows (Figure 22): 1. I2C closed loop trim register SMBA bit is forced to high by internal ispPAC-POWR6AT6 control logic whenever the trim lock status changes 2. ispPAC-POWR6AT6 closed-loop trim control logic pulls the CLTLOCK/SMBA pin low 3. Master responds to interrupt from SMBA line 4. Master broadcasts a read operation by sending the SMBus Alert Response Address (ARA, 18h) 5. ispPAC-POWR6AT6 responds to the ARA request by transmitting its device address
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ispPAC-POWR6AT6 Data Sheet
6. If transmitted device address matches ispPAC-POWR6AT6 address, the master completes the cycle by setting the I2C closed loop trim register SMBA bit low again. This releases the CLTLOCK/SMBA pin (it goes high). Figure 22. SMBAlert Bus Transaction
SMBA SCL SDA
SLAVE ASSERTS SMBA START
1 0
2 0
3 0
4 1
5 1
6 0
7 0
8 R/W
9 ACK
1 A6
2 A5
3 A4
4 A3
5 A2
6 A1
7 A0
8 x
9 ACK
ALERT RESPONSE ADDRESS (0001 100)
SLAVE ADDRESS (7 BITS)
SLAVE RELEASES SMBA
STOP
Note: Shaded Bits Asserted by Slave
After CLTLOCK/SMBA has been released, the bus master (typically a microcontroller) may opt to perform some service functions in which it may send data to or read data from the ispPAC-POWR6AT6. As part of the service functions, the bus master will typically need to clear whatever condition initiated the SMBAlert request (power supply malfunction, etc.). For further information on the SMBus functionality, the user should consult the SMBus Standard.
Software-Based Design Environment
Designers can configure the ispPAC-POWR6AT6 using PAC-Designer, an easy to use, Microsoft Windows compatible program. Circuit designs are entered graphically and then verified, all within the PAC-Designer environment. Full device programming is supported using PC parallel port I/O operations and a download cable connected to the serial programming interface pins of the ispPAC-POWR6AT6. A library of configurations is included with basic solutions and examples of advanced circuit techniques are available on the Lattice web site for downloading. In addition, comprehensive on-line and printed documentation is provided that covers all aspects of PAC-Designer operation. The PAC-Designer schematic window, shown in Figure 23, provides access to all configurable ispPACPOWR6AT6 elements via its graphical user interface. All analog input and output pins are represented. Static or non-configurable pins such as power, ground, and the serial digital interface are omitted for clarity. Any element in the schematic window can be accessed via mouse operations as well as menu commands. When completed, configurations can be saved, simulated, and downloaded to devices. Figure 23. PAC-Designer ispPAC-POWR6AT6 Design Entry Screen
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Lattice Semiconductor
ispPAC-POWR6AT6 Data Sheet
In-System Programming
The ispPAC-POWR6AT6 is an in-system programmable device. This is accomplished by integrating all E2 configuration memory and SRAM control logic on-chip. Programming is performed through a 4-wire, IEEE 1149.1 compliant serial JTAG interface at normal logic levels. Once a device is programmed, all configuration information is stored on-chip, in non-volatile E2CMOS memory cells. The specifics of the IEEE 1149.1 serial interface and all ispPAC-POWR6AT6 instructions are described in the JTAG interface section of this data sheet.
User Electronic Signature
A user electronic signature (UES) feature is included in the E2CMOS memory of the ispPAC-POWR6AT6. This consists of 32 bits that can be configured by the user to store unique data such as ID codes, revision numbers or inventory control data. The specifics of this feature are discussed in the IEEE 1149.1 serial interface section of this data sheet.
Electronic Security
An electronic security "fuse" (ESF) bit is provided in every ispPAC-POWR6AT6 device to prevent unauthorized readout of the E2CMOS configuration bit patterns. Once programmed, this cell prevents further access to the functional user bits in the device. This cell can only be erased by reprogramming the device, so the original configuration cannot be examined once programmed. Usage of this feature is optional. The specifics of this feature are discussed in the IEEE 1149.1 serial interface section of this data sheet.
Production Programming Support
Once a final configuration is determined, an ASCII format JEDEC file can be created using the PAC-Designer software. Devices can then be ordered through the usual supply channels with the user's specific configuration already preloaded into the devices. By virtue of its standard interface, compatibility is maintained with existing production programming equipment, giving customers a wide degree of freedom and flexibility in production planning.
Evaluation Fixture
The Design Kit for the ispPAC-POWR1220AT8, a larger device that contains all the same functions as the ispPACPOWR6AT6, can be used to evaluate the ispPAC-POWR6AT6. Included in the basic ispPAC-POWR1220AT8 Design Kit is an engineering prototype board that can be connected to the parallel port of a PC using a Lattice download cable. It demonstrates proper layout techniques for the ispPAC-POWR1220AT8 which also apply to the ispPAC-POWR6AT6 and can be used in real time to check circuit operation as part of the design process. Input and output connections are provided to aid in the evaluation of either device for a given application. (Figure 24). Figure 24. Download from a PC
PAC-Designer Software
Other System Circuitry
ispDOWNLOAD Cable (6') 4
ispPAC-POWR 1220AT8 Device
IEEE Standard 1149.1 Interface (JTAG)
Serial Port Programming Interface Communication with the ispPAC-POWR6AT6 is facilitated via an IEEE 1149.1 test access port (TAP). It is used by the ispPAC-POWR6AT6 as a serial programming interface. A brief description
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Lattice Semiconductor
ispPAC-POWR6AT6 Data Sheet
of the ispPAC-POWR6AT6 JTAG interface follows. For complete details of the reference specification, refer to the publication, Standard Test Access Port and Boundary-Scan Architecture, IEEE Std 1149.1-1990 (which now includes IEEE Std 1149.1a-1993).
Overview
An IEEE 1149.1 test access port (TAP) provides the control interface for serially accessing the digital I/O of the ispPAC-POWR6AT6. The TAP controller is a state machine driven with mode and clock inputs. Given in the correct sequence, instructions are shifted into an instruction register, which then determines subsequent data input, data output, and related operations. Device programming is performed by addressing the configuration register, shifting data in, and then executing a program configuration instruction, after which the data is transferred to internal E2CMOS cells. It is these non-volatile cells that store the configuration or the ispPAC-POWR6AT6. A set of instructions are defined that access all data registers and perform other internal control operations. For compatibility between compliant devices, two data registers are mandated by the IEEE 1149.1 specification. Others are functionally specified, but inclusion is strictly optional. Finally, there are provisions for optional data registers defined by the manufacturer. The two required registers are the bypass and boundary-scan registers. Figure 25 shows how the instruction and various data registers are organized in an ispPAC-POWR6AT6. Figure 25. ispPAC-POWR6AT6 TAP Registers
CFG_DATA REGISTER (56 BITS) E2CMOS NON-VOLATILE MEMORY
CFG_ADDRESS REGISTER (5 BITS) MULTIPLEXER
UES REGISTER (32 BITS)
IDCODE REGISTER (32 BITS)
BYPASS REGISTER (1 BIT)
INSTRUCTION REGISTER (8 BITS)
TEST ACCESS PORT (TAP) LOGIC
OUTPUT LATCH
TDI
TCK
TMS
TDO
TAP Controller Specifics
The TAP is controlled by the Test Clock (TCK) and Test Mode Select (TMS) inputs. These inputs determine whether an Instruction Register or Data Register operation is performed. Driven by the TCK input, the TAP consists of a small 16-state controller design. In a given state, the controller responds according to the level on the TMS input as shown in Figure 26. Test Data In (TDI) and TMS are latched on the rising edge of TCK, with Test Data Out (TDO) becoming valid on the falling edge of TCK. There are six steady states within the controller: Test-Logic-Reset, RunTest/Idle, Shift-Data-Register, Pause-Data-Register, Shift-Instruction-Register and Pause-Instruction-Register. But there is only one steady state for the condition when TMS is set high: the Test-Logic-Reset state. This allows a reset of the test logic within five TCKs or less by keeping the TMS input high. Test-Logic-Reset is the power-on default state.
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Lattice Semiconductor
Figure 26. TAP States
1 0 Test-Logic-Rst 0 Run-Test/Idle 1 1 Select-DR-Scan 0 Capture-DR 0 Shift-DR 1 Exit1-DR 0 Pause-DR 0 1 Exit2-DR 1 Update-DR 1 0 0 0 1 1
ispPAC-POWR6AT6 Data Sheet
Select-IR-Scan 1 0 Capture-IR 0 Shift-IR 1 Exit1-IR 0 Pause-IR 0 1 Exit2-IR 1 Update-IR 1 0
1
0 1
0
Note: The value shown adjacent to each state transition in this figure represents the signal present at TMS at the time of a rising edge at TCK.
When the correct logic sequence is applied to the TMS and TCK inputs, the TAP will exit the Test-Logic-Reset state and move to the desired state. The next state after Test-Logic-Reset is Run-Test/Idle. Until a data or instruction shift is performed, no action will occur in Run-Test/Idle (steady state = idle). After Run-Test/Idle, either a data or instruction shift is performed. The states of the Data and Instruction Register blocks are identical to each other differing only in their entry points. When either block is entered, the first action is a capture operation. For the Data Registers, the Capture-DR state is very simple: it captures (parallel loads) data onto the selected serial data path (previously chosen with the appropriate instruction). For the Instruction Register, the Capture-IR state will always load the IDCODE instruction. It will always enable the ID Register for readout if no other instruction is loaded prior to a Shift-DR operation. This, in conjunction with mandated bit codes, allows a "blind" interrogation of any device in a compliant IEEE 1149.1 serial chain. From the Capture state, the TAP transitions to either the Shift or Exit1 state. Normally the Shift state follows the Capture state so that test data or status information can be shifted out or new data shifted in. Following the Shift state, the TAP either returns to the Run-Test/Idle state via the Exit1 and Update states or enters the Pause state via Exit1. The Pause state is used to temporarily suspend the shifting of data through either the Data or Instruction Register while an external operation is performed. From the Pause state, shifting can resume by reentering the Shift state via the Exit2 state or be terminated by entering the Run-Test/Idle state via the Exit2 and Update states. If the proper instruction is shifted in during a Shift-IR operation, the next entry into Run-Test/Idle initiates the test mode (steady state = test). This is when the device is actually programmed, erased or verified. All other instructions are executed in the Update state.
Test Instructions
Like data registers, the IEEE 1149.1 standard also mandates the inclusion of certain instructions. It outlines the function of three required and six optional instructions. Any additional instructions are left exclusively for the manufacturer to determine. The instruction word length is not mandated other than to be a minimum of two bits, with only the BYPASS and EXTEST instruction code patterns being specifically called out (all ones and all zeroes respectively). The ispPAC-POWR6AT6 contains the required minimum instruction set as well as one from the optional instruction set. In addition, there are several proprietary instructions that allow the device to be configured and verified. Table 7 lists the instructions supported by the ispPAC-POWR6AT6 JTAG Test Access Port (TAP) controller: 28
Lattice Semiconductor
Table 7. ispPAC-POWR6AT6 TAP Instruction Table
Instruction EXTEST BULK_ERASE PROGRAM_SECURITY DISCHARGE PROGRAM_ENABLE IDCODE UES_READ UES_PROGRAM SAMPLE PROGRAM_DISABLE RESET ERASE_DONE_BIT CFG_VERIFY CFG_ERASE CFG_ADDRESS CFG_DATA_SHIFT CFG_PROGRAM PROGRAM_DONE_BIT BYPASS Command Code 0000 0000 0000 0011 0000 1001 0001 0100 0001 0101 0001 0110 0001 0111 0001 1010 0001 1100 0001 1110 0010 0010 0010 0100 0010 1000 0010 1001 0010 1011 0010 1101 0010 1110 0010 1111 1111 1111 Bulk erase device Program security fuse Fast VPP discharge Enable program mode
ispPAC-POWR6AT6 Data Sheet
Comments External Test - Defaults to BYPASS
Read contents of manufacturer ID code (32 bits) Read contents of UES register from E2CMOS (32 bits) Program UES bits into E2CMOS Sample/Preload - Defaults to BYPASS Disable program mode Resets device (refer to reset command via JTAG or I2C section of this data sheet) Erases the DONE bit only Verify the configuration data Erase just the configuration data Select the configuration address register (4 bits) Configuration data shift (56 bits) Program configuration data Programs the DONE bit Bypass - Connect TDO to TDI
BYPASS is one of the three required JTAG instructions. It selects the Bypass Register to be connected between TDI and TDO and allows serial data to be transferred through the device without affecting the operation of the ispPACPOWR6AT6. The IEEE 1149.1 standard defines the bit code of this instruction to be all ones (111111). The required SAMPLE/ PRELOAD instruction dictates the Boundary-Scan Register be connected between TDI and TDO. The ispPACPOWR6AT6 has no boundary scan register, so for compatibility it defaults to the BYPASS mode whenever this instruction is received. The bit code for this instruction is defined by Lattice as shown in Table 7. The EXTEST (external test) instruction is required and would normally place the device into an external boundary test mode while also enabling the boundary scan register to be connected between TDI and TDO. Again, since the ispPAC-POWR6AT6 has no boundary scan logic, the device is put in the BYPASS mode to ensure specification compatibility. The bit code of this instruction is defined by the 1149.1 standard to be all zeros (000000). The optional IDCODE (identification code) instruction is incorporated in the ispPAC-POWR6AT6 and leaves it in its functional mode when executed. It selects the Device Identification Register to be connected between TDI and TDO. The Identification Register is a 32-bit shift register containing information regarding the IC manufacturer, device type and version code (Figure 27). Access to the Identification Register is immediately available, via a TAP data scan operation, after power-up of the device, or by issuing a Test-Logic-Reset instruction. The bit code for this instruction is defined by Lattice as shown in Table 7.
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Lattice Semiconductor
Figure 27. ispPAC-POWR6AT6 ID Code MSB
ispPAC-POWR6AT6 Data Sheet
LSB
XXXX / 0000 0001 1000 0000 / 0000 0100 001 / 1
Part Number (16 bits) 0180h = ispPAC-POWR6AT6
Version (4 bits) E 2 Configured
JEDEC Manufacturer Identity Code for Lattice Semiconductor (11 bits) Constant 1 (1 bit) per 1149.1-1990
ispPAC-POWR6AT6 Specific Instructions
There are 15 unique instructions specified by Lattice for the ispPAC-POWR6AT6. These instructions are primarily used to interface to the various user registers and the E2CMOS non-volatile memory. Additional instructions are used to control or monitor other features of the device. A brief description of each unique instruction is provided in detail below, and the bit codes are found in Table 7. BULK_ERASE - This instruction will bulk erase the ispPAC-POWR6AT6. The action occurs at the second rising edge of TCK in Run-Test-Idle JTAG state. The device must already be in programming mode (PROGRAM_ENABLE instruction). PROGRAM_SECURITY - This instruction is used to program the electronic security fuse (ESF) bit. Programming the ESF bit protects proprietary designs from being read out. The programming occurs at the second rising edge of the TCK in Run-Test-Idle JTAG state. The device must already be in programming mode (PROGRAM_ENABLE instruction). DISCHARGE - This instruction is used to discharge the internal programming supply voltage after an erase or programming cycle and prepares ispPAC-POWR6AT6 for a read cycle. PROGRAM_ENABLE - This instruction enables the programming mode of the ispPAC-POWR6AT6. IDCODE - This instruction connects the output of the Identification Code Data Shift (IDCODE) Register to TDO (Figure 28), to support reading out the identification code. Figure 28. IDCODE Register
TDO
Bit 31 Bit 30 Bit 29 Bit 28 Bit 27 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
UES_READ - This instruction both reads the E2CMOS bits in the UES register and places the UES register between the TDI and TDO pins (as shown in Figure 29), to support programming or reading of the user electronic signature bits. Figure 29. UES Register
TDO
Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
UES_PROG - This instruction will program the content of the UES Register into the UES E2CMOS memory. The device must already be in programming mode (PROGRAM_ ENABLE instruction). PROGRAM_DISABLE - This instruction disables the programming mode of the ispPAC-POWR6A6. The TestLogic-Reset JTAG state can also be used to cancel the programming mode of the ispPAC-POWR6A6. 30
Lattice Semiconductor
ispPAC-POWR6AT6 Data Sheet
RESET - This command resets the ispPAC-POWR6AT6 to a condition near that of the power-on reset state (refer to reset command via JTAG or I2C section of this data sheet for more details and known exceptions). ERASE_DONE_BIT - This instruction erases the ispPAC-POWR6A6 DONE bit. CFG_VERIFY - This instruction is used to verify the contents of the selected configuration array column. This specific column is preselected by using CFG_ADDRESS instruction. CFG_ERASE - This instruction will bulk erase the configuration array. The action occurs at the second rising edge of TCK in Run-Test-Idle JTAG state. The device must already be in programming mode (PROGRAM_ENABLE instruction). CFG_ADDRESS - This instruction is used to set the address of the configuration array for subsequent program or read operations. CFG_DATA_SHIFT - This instruction is used to shift data into the configuration register prior to programming or reading. CFG_PROGRAM - This instruction programs the selected configuration array column. This specific column is preselected by using CFG_ADDRESS instruction. The programming occurs at the second rising edge of the TCK in Run-Test-Idle JTAG state. The device must already be in programming mode (PROGRAM_ENABLE instruction). PROGRAM_DONE_BIT - This instruction programs the ispPAC-POWR6A6 DONE bit. Note: Before any of the above programming instructions are executed, the respective E2CMOS bits need to be erased using the corresponding erase instruction
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Lattice Semiconductor
ispPAC-POWR6AT6 Data Sheet
Package Diagram
32-Pin QFN
Dimensions in millimeters
2X 0.25 C A 5.00 b 4.75 2X N 3 1 PIN 1 ID 0.25 C B N D2 PIN #1 ID FIDUCIAL LOCATED IN THIS AREA A 4 0.10
M
CA B
1
4.75
5.00
E2
L 0.20 C 2X B B
32X
e 3.5 4X
3
TOP VIEW
0.20 C 2X A
0
A2 A 5 0.08 C A3 A1
BOTTOM VIEW
C
SIDE VIEW
SEATING PLANE
Note: If soldered to the circuit board for thermal considerations, insure the thermal pad is connected electrically to ground. Otherwise, the thermal pad should not be connected electrically (must be left "floating"). For important information on the preferred mounting of QFN packages, refer to the following application note at: http://www.amkor.com/products/notes_papers/MLFAppNote.pdf.
NOTES: UNLESS OTHERWISE SPECIFIED 1. DIMENSIONS AND TOLERANCES PER ANSI Y14.5M. ALL DIMENSIONS ARE IN MILLIMETERS.
SYMBOL A A1 A2
MIN. 0.00 0.00
NOM. 0.85 0.01 0.65 0.20 REF
MAX. 1.00 0.05 1.00
2.
A3
3
EXACT SHAPE AND SIZE OF THIS FEATURE IS OPTIONAL. DIMENSION b APPLIES TO PLATED TERMINAL AND IS MEASURED BETWEEN 0.20 AND 0.25 mm FROM TERMINAL TIP. APPLIES TO EXPOSED PORTION OF TERMINALS.
D2 E2
1.25 1.25
2.70 2.70 0.50 BSC
3.25 3.25
4
e b L 0.18 0.30 -
0.24 0.40 -
0.30 0.50 12
5
0
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Lattice Semiconductor
ispPAC-POWR6AT6 Data Sheet
Part Number Description
ispPAC-POWR6AT6 - 01XX32X
Device Family Device Number Operating Temperature Range I = Industrial (-40oC to +85oC) Package N = 32-pin QFN NN = Lead-Free 32-pin QFN* Performance Grade 01 = Standard
*Contact factory for package availability.
Ordering Information
Conventional Packaging
Part Number ispPAC-POWR6AT6-01N32I Package QFN Pins 32
Lead-Free Packaging
Part Number ispPAC-POWR6AT6-01NN32I Package QFN Pins 32
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Lattice Semiconductor
ispPAC-POWR6AT6 Data Sheet
Package Options
VMON6 TRIM1 TRIM2 TRIM3 TRIM4 TRIM5 TRIM6 GND
32 TDO VCCJ TCK TDI TMS CLTENb VPS0 VPS1 1 2 3 4 5 6 7 8 9
CLTLOCK/SMBA
31
30
29
28
27
26
25 24 VMON6GS 23 VMON5 22 VMON5GS 21 VMON4
ispPAC-POWR6AT6 32-Pin QFN
20 VMON4GS 19 VMON3 18 VMON3GS 17 VMON2
10
SCL
11
SDA
12
VCCD
13
VCCA
14
VMON1GS
15
VMON1
16
VMON2GS
34

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